Scientists develop novel high-fidelity quantum computing gate

The DTC is a new kind of tunable coupler composed of two fixed-frequency transmons -- a type of qubit that is relatively insensitive to noise arising from charge -- coupled through a loop with an additional Josephson junction. Its architecture addresses one of the most pressing challenges in quantum computing: the development of hardware to connect qubits in a high-fidelity way. High gate fidelity is essential for minimizing errors and enhancing the reliability of quantum computations, and the DTC scheme stands out by achieving both suppressed residual interaction and rapid high-fidelity two-qubit gate operations, even for highly detuned qubits. Though fidelity of 99.9 percent has been achieved for single-qubit gates, fault rates for two-qubit devices are typically 1 percent or more, mainly due to interactions between the qubits known as the ZZ interaction.

A key of the current work, published in Physical Review X, is the construction of a gate using state-of-the-art fabrication techniques using a type of machine learning known as reinforcement learning. This approach allowed the researchers to translate the theoretical potential of the DTC into practical application. They used this approach to achieve a balance between two types of remaining error -- leakage error and decoherence error -- that remained within the system, selecting a length of 48 nanoseconds as an optimal compromise between the two error sources. Thanks to this, they were able to achieve fidelity levels that are among the highest reported in the field.

According to Yasunobu Nakamura, director of the RIKEN Center for Quantum Computing, "By reducing the error rates in quantum gates, we have made more reliable and accurate quantum computations possible. This is particularly important for the development of fault-tolerant quantum computers, which are the future of quantum computing."

He continues, "This device's ability to perform effectively with highly detuned qubits makes it a versatile and competitive building block for various quantum computing architectures. This adaptability ensures that it can be integrated into existing and future superconducting quantum processors, enhancing their overall performance and scalability. In the future, we plan to try to achieve a shorter gate length, as this could help minimize the incoherent error."