Circuit technology that resolves issues with high-frequency piezoelectric resonators
Realizing compact, low-cost, high-speed radio communication systems for the IoT age
- Date:
- June 17, 2016
- Source:
- National Institute of Information and Communications Technology (NICT)
- Summary:
- Scientists have developed a new algorithm and circuit technology allowing high-frequency piezoelectric resonators to be used for phase locked loops (PLL). It was confirmed that these operate with low noise and have an excellent Figure of Merit compared to conventional PLLs.
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In collaboration with the National Institute of Information and Communications Technology (NICT), Associate Professor Hiroyuki Ito and Professor Kazuya Masu, et al., of the Tokyo Institute of Technology, developed a new algorithm and circuit technology allowing high-frequency piezoelectric resonators to be used for phase locked loops (PLL). It was confirmed that these operate with low noise and have an excellent Figure of Merit (FoM) compared to conventional PLLs.
This technology allows high-frequency piezoelectric resonators to be used in place of crystal oscillators which was a problem for realizing compact and low-cost radio modules. This greatly contributes to the creation of compact, low-cost, high-speed radio communication systems for the IoT age. High-frequency piezoelectric resonators are compact, can be integrated, have an excellent Q value, and oscillators that use these have excellent jitter performance. High-frequency piezoelectric resonators had greater issues with resonance frequency variance and temperature dependability compared to crystal resonators. However, these issues were resolved by the development of a PLL that uses a channel adjustment technique, which is a new algorithm.
A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world's top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.
The study results will be announced in local time June 17 in "The 2016 Symposium on VLSI Circuits" to be held in Hawaii from June 14.
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Materials provided by National Institute of Information and Communications Technology (NICT). Note: Content may be edited for style and length.
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