Circuit technology that resolves issues with high-frequency piezoelectric resonators

This technology allows high-frequency piezoelectric resonators to be used in place of crystal oscillators which was a problem for realizing compact and low-cost radio modules. This greatly contributes to the creation of compact, low-cost, high-speed radio communication systems for the IoT age. High-frequency piezoelectric resonators are compact, can be integrated, have an excellent Q value, and oscillators that use these have excellent jitter performance. High-frequency piezoelectric resonators had greater issues with resonance frequency variance and temperature dependability compared to crystal resonators. However, these issues were resolved by the development of a PLL that uses a channel adjustment technique, which is a new algorithm.

A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world's top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.

The study results will be announced in local time June 17 in "The 2016 Symposium on VLSI Circuits" to be held in Hawaii from June 14.