Groundbreaking, waterless approach to microchip making

Moore's Law -- the observation by Intel co-founder Gordon E. Moore that the number of transistors on a chip, and as a consequence the processing power, doubles approximately every two years -- has been accurate for more than half a century. Today, we carry more computing power in the mobile phones in our pockets than could fit into a house-sized computer back then. But in order to squeeze more transistors into a smaller space -- and ensure Moore's Law continues to hold true -- chip developers have to be increasingly innovative as chip components are shrinking into the 'nano' scale.

Sometimes they have to think completely outside the box. That was the approach taken by the 'Copper interconnects for advanced performance and reliability' (Copper) project, in which researchers from eight organisations -- companies, research institutes and universities -- in four countries solved a key problem of chip manufacturing. In the process, they have opened the door to an entirely new field of research in the semiconductor industry.

Supported by EUR 3.15 million in funding from the European Commission, the researchers focused on the methods and materials used to interconnect the billions of tiny transistors on a modern microchip. Specifically, the Copper team developed a process that enables reactive metals to be used directly as a barrier between copper interconnects and the silicon wafer of the chip by using non-aqueous solvents instead of water-based ones -- a world first in the semiconductor industry.

'As the number of transistors on a chip increases, so too do the lengths of interconnects between transistors. Because interconnects have a certain resistance, this increase in length causes an increase in the time delay in communication between transistors -- it's an impediment to chip performance,' explains Jan Fransaer, a researcher in the Department of Metallurgy and Materials Engineering (MTM) at the Katholieke Universiteit Leuven in Belgium.

If the interconnects can be made smaller, chip performance improves. But now that chip features have reached the 22nm scale -- around 3,000 times smaller than the width of a human hair -- there are new obstacles to further reductions in length.

The problem in a nutshell

In grossly simplified terms, the problem goes something like this:

Until the mid 1990s aluminium was the metal of choice to fill the interconnect 'vias', the small trenches in the silicon that carry electrons between the transistors. Aluminium was sufficiently conductive to meet the performance requirements of the transistors -- then numbered in the millions on each chip -- and unlike other more conductive metals such as copper, silver and gold it did not diffuse into the silicon, a process that over time would ultimately destroy the circuitry.

But as chips got smaller and their transistor counts increased toward the billions, faster interconnect performance was needed. A more conductive metal had to be used. Hence, semiconductor manufacturers switched to copper as an interconnect material. This in turn required that they do something to prevent the copper diffusing into the silicon, a problem they solved by adding something known as a 'diffusion barrier' -- a layer of another metal that protects the silicon from the copper. The diffusion barrier of choice is a metal called tantalum.

So far, so good: the tantalum diffusion barrier now protects the silicon from the copper in the interconnect vias.

The deposition of the copper interconnects is done by a process called 'electrodeposition' in which an electric current is passed through a solvent solution to coat metal ions onto the vias. An aqueous (i.e. water-based) solution is the usual solvent.

But there's another problem: tantalum oxidises immediately in water, so until now manufacturers have had to first coat the tantalum diffusion barrier with copper -- a so-called seed layer that protects the tantalum from the water just as the tantalum protects the silicon from the copper.

The seed layer is applied using a 'chemical vapour deposition' (CVD) process.

'Why can't we just use the seed layer for the interconnects? Because CVD is a line-of-sight process: it lays down enough copper to coat the tantalum but not enough to make continuous interconnects. So we still have to do electrodeposition on to the copper seed layer to fill the vias with enough copper to make the interconnects,' Prof. Fransaer explains.

In essence, chip manufacturers have been playing 'Russian dolls' at the nanometre scale.

'It sounds stupid -- solving one problem generates another problem -- but this fix has worked ok until now,' Prof. Fransaer notes.

So what has changed? Scale. The copper seed layer is 5nm to 10nm thick, so at scales of less than 22nm that layer -- which serves no other purpose than to protect the tantalum diffusion barrier from oxidisation during chip production -- ends up taking up way too much space.

The answer? 'Change the solvent,' says Prof. Fransaer.

Solving the solvent issue

Instead of using water, the Copper project team developed an innovative process using non-aqueous solvents such as liquid ammonia and ionic liquids. These do not cause tantalum to oxidise, hence allowing electrodeposition to occur without the need for the copper seed layer. The result is that because the interconnect vias can be smaller, chip size can be further reduced, transistor count increased and chip performance greatly improved.

'Electrodeposition using liquid ammonia and ionic liquids has been done before, but this is the first time that this process has been used in the semiconductor industry,' Prof. Fransaer says. 'This technique will certainly help enable a continuation of Moore's Law at least for a few more generations.'

To develop the process, the team studied different wafer materials and electrolyte ingredients for the non-aqueous solution, investigated their physical properties and used analytical and simulation techniques to determine the best approach. They then used micro-modelling of the process before building a proof-of concept demonstrator.

'We were really delving into terra incognita. It was totally uncharted territory, as prior to the Copper project not a single paper had been published on using non-aqueous solutions in the semiconductor industry,' the project manager notes.

Unsurprisingly, the project generated considerable interest from chip makers when the team presented their results at international conferences.

'There was definitely a lot of interest, though we can't say for sure if anyone has used our research as a basis to use this process commercially. Nonetheless, I think it's only a matter of time before non-aqueous solutions start being used now that we've shown it can be done,' Prof. Fransaer says.

Though ammonia -- which needs to be pressurised to stay in liquid form -- or ionic liquids are less abundant and more expensive than water, the cost of using them is a 'non-issue' in the multi-billion euro semiconductor industry, Prof. Fransaer points out.

'Moving from aqueous to non-aqueous solutions would have only a miniscule impact on cost in the grand scheme of things,' he says.

Perhaps even more significantly, the team's research has opened people's eyes to other possibilities, not just with tantalum but also other metals and not just for semiconductor applications.

For example, members of the project consortium are planning a follow-up project using elements of the Copper project's research to work on improving heat dissipation for power electronics, of the sort that will be needed in the smart electricity grids now being rolled out in Europe and elsewhere.

'A lot of elements -- among them all the so-called noble metals -- can be electroplated from water, but a lot can't: aluminium, silicon, germanium etc. We have shown that by using a non-aqueous solution, some of these can also be electroplated. That opens up a whole new range of applications that probably weren't thought possible before,' Prof. Fransaer says.

Copper received research funding under the European Commission's Seventh Framework Programme (FP7).